Source and drain junction regions of field effect transistors can be implanted with a shallow, extension source and drain regions to, for example, reduce punchthrough. Typical tip or extension formation in three-dimensional tri-gate field effect transistor structures involves the use of ion implantation of dopant (e.g., N-type dopant). Challenges associated with such implantation include resulting fin damage, achieving good uniformity or dopant concentration along a height of a fin and time and costs associated with the requirement of lithography patterning prior to such implantation.